The present application is related to U.S. patent application Ser. No. 08/414,919 entitled xe2x80x9cCIRCUIT FOR DETECTING A FAULT IN A CLOCK SIGNAL FOR MICROPROCESSOR ELECTRONIC DEVICESxe2x80x9d filed of even date herewith by the inventors hereof and assigned to the assignee herein, and incorporated by reference herein.
1. Field of the Invention
The present invention relates to a circuit for detecting irregularities in a clock signal of electronic devices containing a microprocessor and non-volatile memory elements.
The present invention concerns specifically two types of electronic device, to wit:
microcontrollers containing EEPROM or FLASH EEPROM non-volatile memories, and
FLASH EEPROM memories using internally a microprocessor for management of the reading, programming and erasing phases.
The following description is given with reference to this field of application only for the purpose of simplifying discussion thereof.
2. Description of the Prior Art
EEPROM and FLASH EEPROM memories are electrically programmable and erasable memory devices and generally comprise inside them a certain number of electrically programmable but not erasable cells. These cells constitute a small memory matrix termed UPROM (Unerasable and Programmable Read Only Memory) which is programmed by the manufacturer of the integrated circuit during testing of the device and is not visible subsequently to the user.
The UPROM is used mainly by a so-called xe2x80x9credundancyxe2x80x9d circuit contained in the memory device. Said circuit permits replacement of the addresses of the rows or columns which are damaged or in any case do not possess the desired characteristics by other rows or columns termed xe2x80x9credundantxe2x80x9d. By means of the UPROM the manufacturer can also set the memory device configuration by choosing among the various possible configurations provided during designing. This flexibility permits suiting the device to the customer""s or market requirements.
It is thus clear that programming these memory cells is entrusted exclusively to the device manufacturer and must not be permitted the user.
However if the FLASH EEPROM is integrated on a microprocessor device or if it contains inside itself a microprocessor for management of the reading, programming and erasure phases it may happen that following occurrence of an irregular situation such as failure of the clock signal, some outputs of the microprocessor are found with random logic levels. This can cause undesired effects in the device such as e.g. programming of one of the UPROM registers and irreversible corruption of the contents thereof.
To reach the high degree of reliability required today of these devices there is a tendency to equip them with circuits designed to prevent or correct any malfunctions thereof or of circuits peripheral thereto. Such malfunctions can occur during normal use of the microcontroller or memory or following incorrect use thereof, e.g. when the correct timings for the signals applied to its inputs are not respected.
In general these circuits have the function of generating a reset signal which reinitializes the microprocessor while holding it in said state until the situation returns to normal.
Generally all electronic devices comprising a microprocessor have a special external reset pin by means of which it is possible to reset the device. Normally this pin, which is connected internally to a so-called xe2x80x9cpull-upxe2x80x9d resistance, is connected externally to a capacitor of appropriate value so as to hold low the logic level on the reset input until the capacitor is charged. However it may happen that in irregular situations such as e.g. if the device is replaced by another without turning off power to the card the-external capacitor remains charged and the new device is not correctly reset.
For this reason many devices contain a circuit known to those skilled in the art as power-on reset.
The operating principle is quite simple since the circuit output changes state and supplies a reset pulse in response to the mere rise of the supply voltage from zero to a value higher than a certain threshold and typically greater than 2,5 to 3 volts for a 5V power supply.
Generally the reset signal is generated in the microcontroller by the circuit just described and is also transferred to the exterior through a special terminal present in the device. It is thus possible to hold even peripheral circuits interfaced with the device in the reset state.
Although advantageous in certain ways this solution exhibits the following serious shortcoming. If, following a failure in the clock signal generating circuit, said signal is interrupted the power-on reset circuit does not intervene and the microcontroller stops in a random and unpredictable state. There can thus occur irregular situations in the microprocessor which can lead e.g. to writing of one of the UPROM registers and irreversible corruption of its contents.
The technical problem underlying the present invention is to provide a circuit capable of detecting clock signal irregularities and having structural and functional characteristics such as to allow increasing the reliability level of the device in which it is integrated and thus overcoming the limitations and shortcomings indicated above with reference to the prior art.
An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor.
The solution idea underlying the present invention is to monitor the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.
The characteristics and advantages of the circuit and method in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings.